TM 11-5895-856-34-1/EE640-CA-MMI-010/E154 CPU/TO 31W2-2T-122-1
RAS has a storage capacity of over two million words
character from the line printer to the processor. IFCU B
with an average access time of 16.6 milliseconds. The
and D each contain a random access storage controller
ADP status and control panel for the MSCPG varies
(RASC). The RASC accesses any given sector and
slightly in its physical configuration from the CSCPG
track address on a random access storage (RAS) unit in
panel. The functions performed, however, are basically
a maximum of 34 milliseconds with an average transfer
the same in both units. The MSCPG power group
rate of 57,000, 32-bit words per second. The RASC also
contains 12 dc/dc converters compared to the nine in
provides pairty checks on command codes and data
the CSCPG. The peripheral interface panel performs
read from the RAS and generates pairty bits for all data
the same function as the electrical interface panel in the
written into memory. The tape transports in the MSCPG
CSCPG. Sections II through VIII provide block diagram
are the same type as those in the CSCPG. The line
level functional descriptions of each of the units that
printers operate in conjunction with the LPCs to provide
comprise the CSCPG and MSCPG.
Significant
an 80-character printout at a rate of 300 lines per
differences that exist between the CSCPG and MSCPG
minute. The RAS assemblies operate in conjunction
are also explained.
with the RASC to provide mass data storage. Each
Section II. AUTOMATIC DATA PROCESSOR
CPU is shown in the CPU block diagram (fig. 2-1).
2-4. General
There are five major blocks in the organization with
The CSCPG and MSCPG each contain two automatic
communication among the blocks, primarily via a data
data processors (ADP). Each ADP contains three
bus. The five blocks are instruction controller, program
major elements: CPU, IOU, and MCMU. The CPU
level controller, arithmetic section, memory interface
provides central program control and performs the
controller, and process registers.
arithmetic functions of the processor, and also initiates
input/output operations. Functional organization of the
2-2
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