TM 11-5895-856-34-1/EE640-CA-MMI-010/E154 CPU/TO 31W2-2T-122-1
CHAPTER 2
FUNCTIONING OF EQUIPMENT
Section I. INTRODUCTION
magnetic tape controller controls the flow of data
2-1. General
between the magnetic tape transports and the
The circuit switch (CS) and message switch (MS)
processors and also performs pairty checks on the data
provide automatic circuit and message switching service
it handles. The teletype controllers provide the interface
for both analog and digital message traffic in tactical
between the processor dc I/O channel and external
and nontactical environments. These systems are
teletypes A and B. The magnetic tape transports
capable of interfacing (to provide concurrent circuit and
(MTTs) communicate with the processors via the MTC
message switching) or operating independently of each
and provide storage and retrieval of data. The tape
other. The Circuit Switch Central Processor Group
transports are utilized to read operational and
(CSCPG) provides overall control for interaction
maintenance programs into the system. The ADP status
between subsystems and units within the AN/TYC-39
and control panel permits status monitoring and control
and AN/TTC-39. The CSCPG and Message Switch
of each of the processors and the power group. The
Central Processor Group (MSCPG) each employ a high-
power group contains eleven dc/dc converters which
speed data processing system and associated peripheral
provide the dc operating voltages for the CSCPG units.
equipment. The CSCPG and MSCPG function as
The electrical interface panel connects the CSCPG
integrated sets of equipment combined with computer
power group to external power and also provides the
programs and associated data for a specific mission
interconnection between the IFCU and the peripheral
achievement capability. This capability, primarily in
equipment.
areas of timeliness, efficiency and accuracy, enables
2-3.
Message Switch Central Processor Group
centralized processing and control of circuit switching
and message switching and routing to accomplish the
(MSCPG)
The MSCPG consists of two processors, four interface
2-2.
Circuit Switch Central Processor Group
control units, eight magnetic tape transports, three line
printers, two random access storage assemblies, an
(CSCPG)
ADP status and control panel, a power group, and a
The CSCPG consists of two processors, an interface
peripheral
interface
panel.
The
functional
control unit, two magnetic tape transports, an automatic
interconnection of the MSCPG is shown in the MSCPG
data processing (ADP) status and control panel, a power
block diagram figure FO-4 and cable interconnection
group, an electrical interface panel, and a MCMU frame
diagram figure FO-5. The two processors are each
assembly.
The functional interconnection of the
composed of a CPU, an IOU, and an MCMU. These
CSCPG is shown in block diagram figure FO-2 and a
components perform the same general functions as
cable interconnection diagram in figure FO-3. The two
described in the preceding paragraph for the CSCPG.
processors are each composed of a central processor
The IFCUs in the MSCPG differ from the IFCU in the
unit (CPU), an input/output unit (IOU), and two mass
CSCPG. Each of the four IFCUs contains an MTC
core memory units (MCMUs). The CPU is responsible
which is the same as the MTC described previously.
for the arithmetic and control functions of the system.
The TTYC contained in IFCU A also performs the same
The IOU controls communication between the CPU and
function as one of the TTYCs contained in the CSCPG.
the peripheral equipments. The MCMU stores and
The MSCPG IFCUs contain three line printer controllers
reads out the information used by the CPU. The
(LPCs), one in IFCU A and two in IFCU C. The LPCs
interface control unit (IFCU) contains a processor-to-
provide the interface between the line printers and the
processor interface (PPI), a magnetic tape controller
two processors. The LPC provides a means for the
(MTC), and two teletype controllers (TTYCs). The
processor to interrogate the status of the line printer and
processor-to-processor interface permits the exchange
of data between the two CSCPG processors. The
2-1