TM 11-5895-856-34-1/E E640-CA-MMI-010/ E154 CPU/TO 31W2-2T-122-1
(7) Memory access protection so that
c. Mass Core Memory Unit.
memory cycles cannot be initiated unless appropriate
(1) Storage capacity. Message Switch-131K
access conditions are satisfied.
words Circuit Switch-262K words.
(8) Parity generation and checking on
(2) Four modes of operation.
memory data transfer.
(3) Thirty-three bit word length (32 data bits
(9) Processing execution fault detection.
and one parity bit).
b. Input/Output Unit.
(4) Contains self-test circuitry capable of
(1) Memory access protection so that
detecting and isolating faults under computer control.
memory cycles cannot be initiated unless appropriate
(5) Nonvolatile storage.
access conditions are satisfied.
(6) Data access time not to exceed 1200 ns.
(2) Queue table which permits stacking of
d. Environmental.
interrupts.
(1) Temperature.
(3) Parity generation and checking of
(a) Normal operating range: 0 to
F
memory data transfers.
+80 .
F
(4) Real-time clocks to generate time of day
(b) Storage and transit: 70F to + 160
and for control of time dependent functions.
F.
(5) Accepts signals from the ADP status and
(c) Low temperature start: -50 .
F
control panel to accommodate the following:
(d) High temperature start: + 125 .
F
(a) Bootstrap program load.
(2) Atmospheric Pressure.
(b) Malfunction indications.
(a) Operating: sea level to 10,000 ft.
(c) Assistance
in
performing
(b) Storage and transit: sea level to
maintenance and troubleshooting.
40,000 ft.
(d) Detection and indication of power
(3) Relative Humidity.
fluctuations and power faults for CPU and IOU.
(a) Operating: 100% up to 86 .
F
(e) Controls to conduct tests of the
5% up to +125 .
F
computer functions and peripherals including detailed
(b) Nonoperating: 100% up to +86 .
F
diagnostic tests.
5% up to + 125 .
F
(f) Monitoring
computer
functions
during normal operations.
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