TM 11-5895-856-34-1/EE640-CA-MMI-010/ E154 C PU/TO 31W2-2T-122-1
Section IV. INPUT/OUTPUT UNIT
2-13. Input/Output Controller
2-12. General
The. input/output controller (IOC) is largely responsible
The input/output unit (IOU) is used by the processor to
for the multiplexing of data between the memory and
provide control and interface between the MCMU and
various other devices. Data transfer is accomplished
peripheral devices. The IOU consists of the input/output
independently of the CPU.
The IOC has direct
controller (IOC), data exchange units, three real-time
communication with the CPU from which it receives
clocks, and ADP status and control panel logic. A block
instructions regarding input/output requirements. These
diagram showing the functional organization of the IOU
instructions usually result in the transfer of one to four
is presented in figure FO-6. All of the IOU device
bytes to or from the designated peripheral device, to
channels have identical capabilities. The possible I/O
determine the device status or to force the device into a
modes are alarm, input word (four 8-bit bytes), output
specific state.
word (four 8-bit bytes), input byte (eight bits), output
byte (eight bits), and inactive. Each device has a
keyword and terminate word which defines the mode as
2-14. Data Exchange Units
well as starting memory location of data and quantity of
Data may be exchanged with peripheral devices from ac
data to be transferred. Devices may interrupt the CPU
input/output channels (IOX) and dc input/output
when an I/O sequence has been completed. The
channels (IOE). The data exchange units perform the
interrupt of any I/O device can be directed to any
interfacing function between the IOC.
program level. All I/O operations are under control of
software through the use of keywords, terminate words,
Each IOX channel has up to eight independent
and I/O commands. These are privileged instructions
peripheral devices attached to it. The IOE channel has
which allow direct commands to be sent to a device, or
the same function as the IOX channel, varying only in its
allow status to be obtained from a device.
The
drive capability.
commands are DEV (device command), DEX (device
a. IOX: 100 meters
command and exit), ITR (input to register command),
b. IOE: 16 meters
and OFR (output from register command). Status
2-15. Real-Time Clocks
information is also available whenever a device
The three real-time clocks are included as part of the
interrupts the computer. All I/O operations on every
IOU for design convenience. The real-time clocks
channel are checked for correct parity. Every byte of
appear to software as three separate peripheral devices
I/O has odd parity. Memory parity is also checked
and are completely under program control. The IOC
whenever data is accessed prior to being sent over the
sees them as high-priority devices which require count
I/O lines, as well as parity being generated when data is
monitoring, but no memory data transfer. All three
input to the memory. A parity error or any other error
clocks have a count resolution of one millisecond.
detection results in an IOU error interrupt.
Each
peripheral device serviced has a fixed deivce address
2-16. ADP Status and Control Panel Logic
and servicing is based on a priority scheme. The
The ADP status and control panel logic interfaces with
hierarchy of priority (highest to lowest) is as follows:
indicators and controls necessary to operate both the
MSCPG
CSCPG
CPU and the IOU.
These include program load
MTTA
MTT
capability, test selection capability and error indicators.
MTT B
TTY A
MTT C
PPI
MTT D
TTY B
RASA
RAS B
LPA
LPC
LPB
TTY
2-6
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