TM 11-5895-856-34-1/ EE640-CA-MMI-010/ E154 CPU/TO 31W2-2T-122-1
Figure 2-1. CPU Block Diagram.
The technique of communicating via the data bus
contained in the instruction controller is the instruction
minimizes the number of connections between the
location counter, which keeps track of the current
blocks shown in figure 2-1. This technique has the
instruction address, and the instruction register and
effect of shortening the signal line lengths, thus reducing
decode logic, in which the instruction being executed is
propagation delays and decreasing susceptibility to
held and the details of the execution decoded.
noise. Each of the blocks shown in figure 2-1 is
discussed in the following paragraphs.
2-6. Program Level Controller
It is within this block that the register representing the
2-5. Instruction Controller
priority queue are updated and checked to determine if
The instruction controller controls the sequence of
the highest priority program available to be run is
operations within the CPU. The instruction controller
actually running. This block also contains the switching
contains the indicator register which contains flags that
program level logic (program activity determination
indicate the status of the data processing system. Also
logic).
2-3
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