TM 11-5895-856-34-1/ E E640-CA-MMI-010/E154 CPU/TO 31W2-2T-122-1
pages may be ordered in any sequence, providing
2-7. Arithmetic Section
flexibility in the organization and relocation of program
The arithmetic section contains a high-speed, 32-bit
and data. The bit, byte, and half-word section logic is
parallel adder as well as variable field extraction and
used to select regularized short fields for processing by
alignment logic which makes possible the variable field
the arithmetic section or for transfer to another block.
operations of the processor.
The variable field
This capability to select directly 1, 8, or 16 bits from a
operations are utilized to pack the memory data fields
32-bit word, complements the variable field capability of
and also to provide the flexibility of data processing on a
the arithmetic section and permits complete flexibility in
bit, byte, or half-word basis.
the storage and processing of data files.
2-8. Memory Interface Controller
2-9. Process Registers
The memory interface controller contains the memory
Sixteen 32-bit registers are available to the active
address and memory data registers normally associated
program level. These are held in 32, 16-bit random
with a memory CPU interface. It also contains other
access integrated circuit packages which operate with a
special registers and logic which provide processor
cycle time of 200 nanoseconds. These high-speed
addressing and data access. The page control and
memory elements may be used as accumulators, as
address registers contain the 16-page addresses
index registers, or to hold instructions during the
associated with the active program level. Each page
execution of program loops.
address provides access to 2,048, 32-bit words. The
Section III. MASS CORE MEMORY UNIT
interface logic which permits, in the CSCPG, two-port
2-10. General
operation from the CPU or IOU, and, in the MSCPG,
Each mass core memory unit (MCMU) provides random
four-port operation from the RASC, CPU, or IOU. The
access, high-speed, core memory for the associated
MCMU has a 2.5-microsecond memory response cycle
processor. The MCMU provides a memory storage
time and a 1600-nanosecond data access time.
capacity of 131,072 x 33-bit words of non-volatile
Functional organization of the MCMU is shown in the
storage. Each MCMU has a unique address by which it
responds to commands from the CPU, IOU, and, in the
MSCPG, the RASC. Each MCMU also has processor
2-4