TM 11-5805-715-34/EE119-DB-MMI-010/E154 CV3478/TO 31W2-2TTC39-12
2-7. Band Elimination Filter (BEF)
2-6. Receive Logic and Timing
(fig. FO-2)
(fig. FO-2)
The band elimination filter FL1A restricts the SF
The receive logic and timing provides an initial
signaling tone (2600 Hz) to a single trunk and is
guarding interval of time before considering the
switched in and out of the receive path by analog
absence of low-level 2600-Hz tone valid. This
gates U6D and U6E under control of the receive
provides protection against radio fades. In addition
logic (signal processor U6A).
The BEF also
to reporting the absence of low-level SF tone, the
prevents the subscriber from hearing the SF
receive logic also switches the channel sensitivity
signaling tone mixed with audible information
from low-level to high-level by switching analog
signals or recorded announcements. The BEF is
gate U6B on and U6C off. Thirty milliseconds after
inserted into the transmission path within 35 msec
the initial 140 millisecond integration period during
of receipt of the SF tone from amplifier U1 and
which low-level SF tone is not present, the receive
removed within 25 msec of absence of the SF tone.
logic starts to track the incoming SF signal. Once
The BEF is inserted when either the high tone is
tracking has commenced, the absence of high level
present or the low tone is present and not being
SF tone is regarded as the OFF-HOOK or SEIZE
tracked by the logic. The BEF is removed at all
state and the presence of high-level SF tone is
other times.
regarded as the ON-HOOK or RELEASE state.
The receive logic stops tracking and switches the
receiver sensitivity back to low-level (U6C on and
2-8. Timing Circuits
U6B off) after receiving high-level SF tone for a
(fig. FO-5)
minimum of 260 msec. The ON-HOOK state will
be maintained until the low-level SF tone is absent
The clock signals required to operate the receive
(OFF-HOOK) again for at least 140 msec. The
and transmit logic in the NIU are generated on
ON-HOOK and OFF-HOOK state condition is
common equipment card NIU-CE. The 32 kHz and
passed to the foreign NIU over XXY as follows:
500 Hz clock frequencies are derived from the 512
kHz reference oscillator Z3 and 4-bit counters U1,
State
Resistance Into SXY
U2 and U3. The 32 kHz and 500 Hz clocks are
applied to 4-bit counter U10 and decoder U5 on
ON-HOOK
> 100 kohms
circuit card NIU-B2. The clock signals are then
OFF-HOOK
< 100 ohms
applied to signal processor U6A on card NIU-A and
transmit controller U12 on circuit card NIU-B2. A
No state change will pass unless the duration
power on clear circuit, Q1 and U4A, permits
exceeds 22 msec as determined by the integrator
resetting the clock logic to the idle state during
circuit consisting of U1, U7, and U8 located on the
system startup.
transmit card. False state changes are, thus, pre-
vented from being sent across the interface.
2-9. Signal and Test Generators
(fig. FO-5)
The 2600 Hz signaling frequency and 1050 Hz test
frequency are generated on common equipment
card NIU-CE by crystal oscillators Z1 and Z2
respectively and applied to receive card NIU-A and
transmit card NIU-B2 as described in paragraphs
2-5
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